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Content Tagged with Fedora-Core + EDA

EDA: standard cells for chip design

A standard cell is group of transistor and interconnect structures, which provides a boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). All CAD tools for chip design (whether proprietary or open source) require standard cell libraries. These standard cell libraries contain primitive cells required for digital design.

A fedora user will have some standard cell libraries from
  • the alliance package
  • the pharosc package

  • # yum install pharosc\*

    Pharosc provides five new open source standard cell libraries, the vsclib, wsclib, vxlib, vgalib and rgalib. They have been drawn with the Graal software from Alliance, part of an extensive open source software suite for designing integrated circuits with a standard cell design methodology.

    The libraries have been characterized in a generic 0.13µm technology, compatible with most foundry rules. Pharosc is the result of a book that Graham Petley is writing, The Art of Standard Cell Library Design.

    Among the standard cells from pharosc there are many scripts to provide interoperability between magic, alliance and xcircuit as well as scripts to allow one to update actual cells or create his/her own cells (pharosc-devel). There are more than 500 spice decks which can be simulated with either gnucap or ngspice.

    Each single component in any standard cell library comes with a well documentation html manual.
    The latter entails schematics, layouts and several parameters for spice simulation. The transistor schematics for the libraries have been drawn with Xcircuit, which uses Postscript as its native file format.

    Pharosc entails Alliance's sxlib which has been characterised in 0.13µm using the same methodology and converted to the same 0.13µm layout rules. There is also an ssxlib which is the Alliance sxlib converted with a script from 1µm to 2µm layout and adjusted to obey DSM layout rules. The adjustments change the timing slightly.

    Fedora-Core: Open Source Fedora Core Blog

    EDA: Physical Layout is done, so what's next? (PART_2)

    In EDA: Physical Layout is done, so what's next? (PART_1), I talked about interoperability between opensource Layout Editors which Fedora is shipping or will ship soon:
  • alliance (soon on fedora)
  • magic
  • toped
  • with the GDS II stream format (GDSII) or Caltech Intermediate Form (CIF) provided the proper technology has been fed.

    In Part_2, I'll demonstrate
  • with an Invertor (TSMC 0.25µm SCN5M_DEEP technology) how with magic I can exchange my layout with toped using the GDS II stream format (GDSII) (I believe you can do the same with CIF on your own) and
  • what I can do next with gds2pov which was recently included.
  • Here's a graphical overview of what I'm talking about and it also defines the wafer fabrication's position in the process:

    The opensource tools are described in blue.

    I've already created the layout of the invertor (both NMOS and PMOS: w=0.48µm l=0.24µm) and available here.

    Open magic with:
    magic -TSCN5M_DEEP.12.light -dOGL &
    Lambda is the unit length in magic layout. It is a visible square box in the grid mode of magic. Since the minimum size of a ploy (red) area (which is also the possible minimum size of magic) is 2 lambda, the length of lambda is half of the technology size.

    When using TSMC 0.25µm, 1 lambda = 0.25µm/2 = 0.12µm

    Have a look at the Tech Manager:

    _THEN_ open the layout: invertor_lay.mag
    Convert the layout to GDSII format with "File -> Write GDS".
    Now that you have a GDSII data file, you can import it on "toped".
    Once your layout has been completed and appropriate checks have been made, you can either send for wafer fabrication or view it in 3D with gds2pov.

    gdsoglviewer -p pov_process.txt -i invertor_0u25.gds P+ -c pov_config.txt

    I update the pov_process to fit the technology I'm using. However the height of each layer doesn't show the real fabrication's heights. The pov_process file defines the Layer Maps of my GDSII data files. For the TSMC 0.25µm SCN5M_DEEP technology I used these Layers are described on MOSIS SCMOS Technology Codes and Layer Maps :SCN5M, SCN5M_SUBM,and SCN5M_DEEP
    Use your mouse to rotate and zoom (right click = zoom out and left click zoom in).
    This is a mere simple example that does nothing more than:
  • when input is 1 output is 0
  • when input is 0 output is 1
  • Fedora-Core: Open Source Fedora Core Blog