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Content Tagged with Fedora-Core + electronics
Fedora Electronic Lab 8 - Stable release
Last Thursday, 8th November 2007, the very first Fedora Electronic Lab LiveCD was released officially. This LiveCD is based on Fedora 8 KDE along with almost all electronic design tools.
Fedora's Electronic Laboratory provides a complete electronic laboratory setup with reliable open source design tools in order to meet one's requirements to keep one in pace with current technological race. Project management tools such as spreadsheet, gantt diagram, mindmapping tools.... are also included. This Electronic Laboratory can either be deployed by:
Download Fedora Electronic Lab LiveCD NOW via torrent
Read the abstract, the flyer or its website for more details.
For Fedora 8's release, "Fedora Electronic Lab" targets mainly the Micro-Nano Electronic Engineering field. It introduces:
Fedora's Electronic Laboratory provides a complete electronic laboratory setup with reliable open source design tools in order to meet one's requirements to keep one in pace with current technological race. Project management tools such as spreadsheet, gantt diagram, mindmapping tools.... are also included. This Electronic Laboratory can either be deployed by:
- yum or
- a Fedora Electronic Lab LiveCD
Download Fedora Electronic Lab LiveCD NOW via torrent
Read the abstract, the flyer or its website for more details.
For Fedora 8's release, "Fedora Electronic Lab" targets mainly the Micro-Nano Electronic Engineering field. It introduces:
- tools for Application-Specific Integrated Circuit (ASIC) Design Flow process to the Fedora Collection.
- extra open source standard cell libraries supporting a feature size of 0.13µm. (more than 300 MB)
- extracted spice decks which can be simulated with gnucap/ngspice or any spice simulators.
- interoperability between various packages in order to achieve different design flows.
Fedora Electronic Lab Live CD Test 3
Fedora Electronic Lab Live CD Test 3 was released yesterday.
Use get-fedora wiki page to download a copy.
Use get-fedora wiki page to download a copy.
EDA: Physical Layout is done, so what's next? (PART_1)
Whether you are a student, lecturer, VLSI amateurs or professionals, there is no way that you can prevent yourself from using proprietary softwares such from Cadence, Altera...
In the semiconductor world, students/trainees are taught under proprietary softwares so as they could be attractive for companies recruiting them. Similarly, students studying accounting or economics are taught under Microsoft Office instead of OpenOffice for the same reason. Sadly, this is the truth.
However proprietary softwares for the semiconductor world are so expensive that one can't afford for personal use (much more expensive than Vista, to give you an idea). Opensource might be an alternative. Thereby, the question of exchanging one's work between applications raises. I'll talk about layout editors for now. Each layout editor has its own file format. It would be useless to design a layout if one can't do much with its design. By useless, I mean waste of time and money. Mature EDA CADs like magic and alliance (soon on fedora) do provide exports to the GDS II stream format (GDSII) or Caltech Intermediate Form (CIF) provided the proper technology has been fed.
Now, students can design at home with magic, alliance (soon on fedora) or toped on their Fedora. Then demonstrate their achievement on Cadence's Virtuoso at school, for example. But on Fedora, one isn't only restricted to Layout editing, but can also: extract spice netlists, simulate the latter with ngspice or gnucap (we will soon see gspiceui and gwave into the fedora collection in the next 2 weeks) do Switch-level simulation with irsim do VHDL simulations with either ghdl and freehdl along with gtkwave. do large analog or mixed-signal circuits simulations do schematics with xcircuit, xsch or gschem design pcb with the couple geda suite and pcb. or with kicad and view under gerbv do LVS with alliance (soon on fedora)- However for now netgen is giving segmentation faults. .. (not semiconductor related: gpasm, gpsim, piklab, ktechlab and pikloops useful for pic programming)
All these to say, Fedora has included and will continue to include big opensource names in terms of electronic simulations. By F8's release, alliance, gspiceui and gwave will be available on the fedora collection, making electronic simulations one of F8's features. If you feel something is missing in Fedora's Electronic Simulation Kit or simply give feedbacks, please drop me a mail (chitlesh [AT] fedoraproject DOT org). I'll be delighted to make Fedora provide an Electronic Simulation Kit with which one can do _real_ job!
In Physical Layout is done, so what's next? (PART_2), I'll demonstrate an example of invertor using the TSMC 0.25µm SCN5M_DEEP technology.
In the semiconductor world, students/trainees are taught under proprietary softwares so as they could be attractive for companies recruiting them. Similarly, students studying accounting or economics are taught under Microsoft Office instead of OpenOffice for the same reason. Sadly, this is the truth.
However proprietary softwares for the semiconductor world are so expensive that one can't afford for personal use (much more expensive than Vista, to give you an idea). Opensource might be an alternative. Thereby, the question of exchanging one's work between applications raises. I'll talk about layout editors for now. Each layout editor has its own file format. It would be useless to design a layout if one can't do much with its design. By useless, I mean waste of time and money. Mature EDA CADs like magic and alliance (soon on fedora) do provide exports to the GDS II stream format (GDSII) or Caltech Intermediate Form (CIF) provided the proper technology has been fed.
Now, students can design at home with magic, alliance (soon on fedora) or toped on their Fedora. Then demonstrate their achievement on Cadence's Virtuoso at school, for example. But on Fedora, one isn't only restricted to Layout editing, but can also:
All these to say, Fedora has included and will continue to include big opensource names in terms of electronic simulations. By F8's release, alliance, gspiceui and gwave will be available on the fedora collection, making electronic simulations one of F8's features. If you feel something is missing in Fedora's Electronic Simulation Kit or simply give feedbacks, please drop me a mail (chitlesh [AT] fedoraproject DOT org). I'll be delighted to make Fedora provide an Electronic Simulation Kit with which one can do _real_ job!
In Physical Layout is done, so what's next? (PART_2), I'll demonstrate an example of invertor using the TSMC 0.25µm SCN5M_DEEP technology.
EDA: Physical Layout is done, so what's next? (PART_2)
In EDA: Physical Layout is done, so what's next? (PART_1), I talked about interoperability between opensource Layout Editors which Fedora is shipping or will ship soon:
alliance (soon on fedora) magic toped with the GDS II stream format (GDSII) or Caltech Intermediate Form (CIF) provided the proper technology has been fed.
In Part_2, I'll demonstrate with an Invertor (TSMC 0.25µm SCN5M_DEEP technology) how with magic I can exchange my layout with toped using the GDS II stream format (GDSII) (I believe you can do the same with CIF on your own) and what I can do next with gds2pov which was recently included. Here's a graphical overview of what I'm talking about and it also defines the wafer fabrication's position in the process:
The opensource tools are described in blue.
I've already created the layout of the invertor (both NMOS and PMOS: w=0.48µm l=0.24µm) and available here.
Open magic with:
magic -TSCN5M_DEEP.12.light -dOGL &
Lambda is the unit length in magic layout. It is a visible square box in the grid mode of magic. Since the minimum size of a ploy (red) area (which is also the possible minimum size of magic) is 2 lambda, the length of lambda is half of the technology size.
When using TSMC 0.25µm, 1 lambda = 0.25µm/2 = 0.12µm
Have a look at the Tech Manager:
_THEN_ open the layout: invertor_lay.mag
Convert the layout to GDSII format with "File -> Write GDS".
Now that you have a GDSII data file, you can import it on "toped".
Once your layout has been completed and appropriate checks have been made, you can either send for wafer fabrication or view it in 3D with gds2pov.
gdsoglviewer -p pov_process.txt -i invertor_0u25.gds P+ -c pov_config.txt
I update the pov_process to fit the technology I'm using. However the height of each layer doesn't show the real fabrication's heights. The pov_process file defines the Layer Maps of my GDSII data files. For the TSMC 0.25µm SCN5M_DEEP technology I used these Layers are described on MOSIS SCMOS Technology Codes and Layer Maps :SCN5M, SCN5M_SUBM,and SCN5M_DEEP
Use your mouse to rotate and zoom (right click = zoom out and left click zoom in).
This is a mere simple example that does nothing more than:when input is 1 output is 0 when input is 0 output is 1
In Part_2, I'll demonstrate
The opensource tools are described in blue.
I've already created the layout of the invertor (both NMOS and PMOS: w=0.48µm l=0.24µm) and available here.
Open magic with:
magic -TSCN5M_DEEP.12.light -dOGL &
Lambda is the unit length in magic layout. It is a visible square box in the grid mode of magic. Since the minimum size of a ploy (red) area (which is also the possible minimum size of magic) is 2 lambda, the length of lambda is half of the technology size.
When using TSMC 0.25µm, 1 lambda = 0.25µm/2 = 0.12µm
Have a look at the Tech Manager:
_THEN_ open the layout: invertor_lay.mag
Convert the layout to GDSII format with "File -> Write GDS".
Now that you have a GDSII data file, you can import it on "toped".
Once your layout has been completed and appropriate checks have been made, you can either send for wafer fabrication or view it in 3D with gds2pov.gdsoglviewer -p pov_process.txt -i invertor_0u25.gds P+ -c pov_config.txt
I update the pov_process to fit the technology I'm using. However the height of each layer doesn't show the real fabrication's heights. The pov_process file defines the Layer Maps of my GDSII data files. For the TSMC 0.25µm SCN5M_DEEP technology I used these Layers are described on MOSIS SCMOS Technology Codes and Layer Maps :SCN5M, SCN5M_SUBM,and SCN5M_DEEP
Use your mouse to rotate and zoom (right click = zoom out and left click zoom in).
This is a mere simple example that does nothing more than: