Cache Coherency, Memory Models and Related Things on Popular Architectures

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Some references on cache coherency and memory models, that recently
came up on the Java concurrency mailing list.  The below is based on
the original list is by Jaroslav Sevcik with slight additions...

*Intel Itanium:*  "A Formal Specification of Intel Itanium Processor Family Memory Ordering":http://www.intel.com/design/itanium/downloads/25142901.pdf

*Intel IA-64 (x86), AMD:*

* "Intel 64 Architecture Memory Ordering White Paper":http://www.intel.com/products/processor/manuals/318147.pdf
   * "Richard Hudson's talk on IA memory ordering":http://www.youtube.com/watch?v=WUfvvFD5tAA.

*Sparc TSO:*  "The SPARC Architecture Manual, Version v9":http://www.sparc.org/standards/SPARCV9.pdf

*Java Memory Model:*

* "Java Language Specification, Third Edition, chapter 17, Memory Model":http://java.sun.com/docs/books/jls/third_edition/html/memory.html
   * "Doug Lea's JSR-133 Cookbook":http://g.oswego.edu/dl/jmm/cookbook.html

*Miscellaneous:*

* PhD dissertation of Jalal Kawash: "Limitations and Capabilities of Weak Memory Consistency Systems":http://pages.cpsc.ucalgary.ca/~kawash/papers/dissertation.pdf
   * Shavit and Herlihy:  "The Art of Multiprocessor Programming":http://www.amazon.com/gp/product/0123705916/ref=s9_asin_title_2_subs_c5_29_26_17_16_13-qvfp_p-2785_g1?pf_rd_m=ATVPDKIKX0DER&pf_rd_s=center-2&pf_rd_r=0H07DVEQN6HW88J6ZW0Y&pf_rd_t=101&pf_rd_p=278240301&pf_rd_i=507846

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created on 13 Mar 2008, by jerryk (67.182.142.194)

Some references on cache coherency and memory models, that recently came up on the Java concurrency mailing list. The below is based on the original list is by Jaroslav Sevcik with slight additions…

Intel Itanium: A Formal Specification of Intel Itanium Processor Family Memory Ordering

Intel IA-64 (x86), AMD:

Sparc TSO: The SPARC Architecture Manual, Version v9

Java Memory Model:

Miscellaneous:

PhD dissertation of Jalal Kawash: Limitations and Capabilities of Weak Memory Consistency Systems
Shavit and Herlihy: The Art of Multiprocessor Programming

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